Voltage-aware adaptive static random access memory (SRAM) write assist circuit
US9508420B1 · kind B1 · utility
16Cited by
8References
15Claims
0Family size
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Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.