Method and structure for forming gate contact above active area with trench silicide
US9508825B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including an active area; a gate formed on the active area and surrounded by a spacer along a sidewall; a first source/drain contact and a second source/drain contact positioned on opposing sides of the gate and in contact with the active area; a first recess formed in the first source/drain contact and a second recess formed in the second source/drain contact; a gate contact including a conductive material on and in contact with the gate and the spacer; and an insulating liner disposed along a sidewall of the gate contact and in the first recess in the first source/drain contact and the second recess in the second source/drain contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.