Technique for computational nested parallelism
US9513975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2012 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Mar 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.