Patent · US Active

Using error correcting codes for parity purposes

US9513987B2 · kind B2 · utility

1Cited by

5References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Son T. Dao · Stuttgart, DE
Juergen Haess · Schenefeld, DE
Michael Klein · Schenefeld, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Nov 7, 2014
Grant date	Dec 6, 2016
Priority date	—
Expiry date	Nov 7, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH04L49/557
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.