Patent · US Active

Process for fabricating SOI transistors for an increased integration density

US9514996B2 · kind B2 · utility

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18Claims

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Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Francois Andrieu · Meylan, FR
Denis Rideau · Grenoble, FR

Key dates

Filing date	Apr 15, 2016
Grant date	Dec 6, 2016
Priority date	—
Expiry date	Apr 15, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0172
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A process for fabricating field-effect transistors, including providing a first semiconductor band surmounted with a first semiconductor layer; providing a second semiconductor band surmounted with a second semiconductor layer; providing a buried insulating layer; providing a deep trench isolation passing through the buried insulating layer and isolating the first semiconductor band from the second semiconductor band; etching the first semiconductor band so as to form a first row of semiconductor islands; etching the second semiconductor band so as to form a second row of semiconductor islands; and forming sacrificial gates on the first semiconductor layer and on the second semiconductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.