Vertical NAND and method of making thereof using sequential stack etching and landing pad
US9515080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Apr 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.