Memory structure and manufacturing method of the same
US9515258B2 · kind B2 · utility
3Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.