Etch bias control
US9520299B2 · kind B2 · utility
0Cited by
7References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method for forming a semiconductor device are presented. The method includes providing a patterned reticle having a pattern perimeter defined by active and dummy patterns. The dummy patterns include dummy structures modified according to a density equation. The patterned reticle is used to pattern a resist layer on a substrate with a device layer. An etch is performed to pattern the device layer using the patterned resist layer. Additional processing is performed to complete formation of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.