Integrated circuit comprising PMOS transistors with different voltage thresholds

US9520330B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• International Business Machines Corporation · US

Inventors

• Francois Andrieu · Meylan, FR
• Nicolas Degors · Meylan, FR
• Pierre Perreau · Grenoble, FR

Key dates

• Filing date: Dec 22, 2015
• Grant date: Dec 13, 2016
• Expiry date: Dec 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon—germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon—germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.