Controlling on-state current for two-terminal memory
US9520561B1 · kind B1 · utility
9Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.