Specialized memory disambiguation mechanisms for different memory read access types
US9524164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2013 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (STL) data forwarding. The control logic marks the detected load instruction as a second type responsive to predicting the load instruction has low locality and is not a candidate for STL data forwarding. The control logic processes a load instruction marked as the first type as if the load instruction is dependent on an older store operation. The control logic processes a load instruction marked as the second type as if the load instruction is independent on any older store operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.