Method for decomposing a layout of an integrated circuit
US9524361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | May 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.