Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
US9524955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2012 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.