Channel-last replacement metal-gate vertical field effect transistor
US9525064B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
Abstract
A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain over the sacrificial gate material; depositing a dielectric material on the drain to form a spacer that protects the epitaxial growth; and removing the sacrificial gate material and replacing the sacrificial gate material with a gate stack that surrounds the channel region between the doped source and the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.