Semiconductor structure with lamella defined by singulation trench

US9527725B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Boris Binder · Dresden, DE
• Bernd Foeste · Dresden, DE
• Thoralf Kautzsch · Dresden, DE
• Stefan Kolb · Unterschleißheim, DE
• Marco Mueller · Villach, AT

Key dates

• Filing date: Apr 16, 2014
• Grant date: Dec 27, 2016
• Expiry date: Jun 27, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G01L15/00
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.