Patent · US Active

Systems and methods for test time outlier detection and correction in integrated circuit testing

US9529036B2 · kind B2 · utility

2Cited by

29References

18Claims

0Family size

Assignee

OPTIMAL PLUS LTD. · IL

Inventors

Gil Balog · Jerusalem, IL
Reed Linde · Cameron Park, US
Avi Golan · Nes Ziona, IL

Key dates

Filing date	Sep 22, 2014
Grant date	Dec 27, 2016
Priority date	—
Expiry date	Feb 21, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318511
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.