Power grid segmentation for memory arrays
US9529533B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.