ECC word configuration for system-level ECC compatibility
US9529672B2 · kind B2 · utility
5Cited by
1References
20Claims
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Key dates
| Filing date | Sep 25, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.