Standard cell library with DFM-optimized M0 cuts
US9529954B1 · kind B1 · utility
7Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2016 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Mar 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/985
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 layer is disclosed, along with wafers, chips and systems constructed from such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.