NAND boosting using dynamic ramping of word line voltages
US9530506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.