Operating method of memory device
US9530511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.