Select gate defect detection
US9530514B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2016 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may comprises a transistor having an adjustable threshold voltage. An operation configured to change a threshold voltage of one select transistor and to maintain a threshold voltage of an adjacent select transistor may be performed. The select transistors may be flagged in response to the threshold voltage of either select transistor failing to meet a target threshold voltage in response to the operation. The operation may be an erase operation or a program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.