Devices including ultra-short gates and methods of forming same
US9530647B2 · kind B2 · utility
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3References
23Claims
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Key dates
| Filing date | Sep 25, 2013 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Sep 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.