Semiconductor devices having hybrid stacking structures and methods of fabricating the same
US9530706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Mar 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.