Patent · US Active

Methods of forming vertical transistor devices with self-aligned replacement gate structures

US9530863B1 · kind B1 · utility

54Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 13, 2016
Grant dateDec 27, 2016
Priority date
Expiry dateApr 13, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/151

Abstract

One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.