Latency-aware memory control
US9535627B2 · kind B2 · utility
2Cited by
1References
21Claims
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Key dates
| Filing date | Oct 2, 2013 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Mar 12, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.