IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
US9535849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2009 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.