Patent · US Active

Method of making integrated circuit

US9536781B2 · kind B2 · utility

0Cited by
0References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 20, 2015
Grant dateJan 3, 2017
Priority date—
Expiry dateSep 24, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.