Self-aligned gate-first VFETs using a gate spacer recess
US9536793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2016 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor region; forming a gate-dielectric and metal-spacer consecutively on each side of each fin-structure; forming a liner on all exposed surfaces of the hardmask, gate-dielectrics, and metal-spacers and the substrate; forming an ILD filling spaces between the fin-structures and coplanar with an upper surface of the liner; removing the liner over the fin-structures; removing the hardmask and recessing the liner, the gate-dielectrics and metal-spacers of each fin-structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal-spacers and liners in each cavity; forming a top S/D structure over the gate-dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.