Bond pad structure for low temperature flip chip bonding
US9536848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06527
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.