FinFET with constrained source-drain epitaxial region
US9536879B2 · kind B2 · utility
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8References
5Claims
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Key dates
| Filing date | Jul 9, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jul 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.