Hardware profiling mechanism to enable page level automatic binary translation
US9542191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.