Patent · US Active

Method and apparatus for selecting data path elements for cloning

US9542523B2 · kind B2 · utility

1Cited by

10References

13Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Michael Priel · Netanya, IL
Asher Berkovitz · Kiryat Ono, IL
Slavaf Fleshel · Ashkelon, IL
Amir Grinshpon · Nes Ziona, IL
Dan Kuzmin · Givat Shmuel, IL
Yoav Miller · Rehovot, IL

Key dates

Filing date	Sep 14, 2012
Grant date	Jan 10, 2017
Priority date	—
Expiry date	Sep 17, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3312
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.