Partial block erase for block programming in non-volatile memory
US9543023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.