Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure
US9543405B2 · kind B2 · utility
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6References
19Claims
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Key dates
| Filing date | Mar 28, 2014 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Apr 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
Abstract
A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.