Methods for fabricating high-density integrated circuit devices
US9547740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2014 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Dec 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.