Methods, apparatus, and system for using filler cells in design of integrated circuit devices
US9547741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Nov 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.