Self aligned via and pillar cut for at least a self aligned double pitch
US9548243B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5329
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.