Packaged semiconductor chips with array
US9548254B2 · kind B2 · utility
1Cited by
100References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.