MRAM integration with low-K inter-metal dielectric for reduced parasitic capacitance
US9548333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2014 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.