Methods of fabricating an F-RAM
US9548348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.