Method of using a sacrificial gate structure to make a metal gate FinFET transistor

US9548361B1 · kind B1 · utility

Assignee

• STMICROELECTRONICS, INC. · US

Inventors

• Nicolas Loubet · Guilderland, US
• Pierre Morin · Albany, US

Key dates

• Filing date: Jun 30, 2015
• Grant date: Jan 17, 2017
• Expiry date: Jun 30, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.