Low-latency timing control
US9549100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | Jan 17, 2017 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/73
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.