Packaged electronic device having reduced parasitic effects and method
US9552999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Dec 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.