Interconnect structure having smaller transition layer via
US9553043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.