Wafer backside redistribution layer warpage control
US9553058B1 · kind B1 · utility
4Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a network of RDL lines on the backside of a thinned TSV die to control warpage and the resulting device are provided. Embodiments include providing a thinned TSV die of a 3D IC stack, the thinned TSV die having a front side and a back side; forming a plurality of RDL lines across the backside of the die; and forming a plurality of UBM structures across the backside of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.