Wiring bond pad structures
US9553061B1 · kind B1 · utility
2Cited by
9References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Nov 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure includes: bond pads in an active region of a chip; test pad structures in a kerf region of the chip; and hardmask material in the kerf region between the test pad structures and the bond pads. The surfaces of the test pad structures and the bond pads are devoid of the hardmask material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.