Method and process for integration of TSV-middle in 3D IC stacks
US9553080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.