Magnetic tunnel junction stack alignment scheme
US9553129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2015 |
| Grant date | Jan 24, 2017 |
| Priority date | — |
| Expiry date | Sep 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark. The various layers of the MTJ stack are patterned to form a MTJ element using the alignment mark visible in top surface of the various layers of the MTJ stack to align the memory element to the underlying via plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.