High-speed serial data interface for a physical layer interface
US9557766B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2014 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In an apparatus relating generally to the communication of data, a first and a second receive path block are respectively coupled to receive a first and a second data stream. A clock signal source is coupled to provide at least one clock signal to each of the first and the second receive path block. A control block is coupled to receive a first output signal pair and a second output signal pair from the first and the second receive path block, respectively. The first output signal pair includes a first crossing signal and a first data signal. The second output signal pair includes a second crossing signal and a second data signal. The control block is configured to provide first and second delay adjustment signals respectively to the first and second receive path blocks, to adjust delays of the first and second data streams, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.